Method for Manufacturing a Semiconductor Device

ABSTRACT

A manufacturing method of a semiconductor device wherein a metal pad is etched to form a trench in which a central part is concave in form, or to form a trench in the shape of a cylinder or a parallelepiped on the edge part of a metal pad. Accordingly, the contact area between a polymide isoindro quirazorindione (PIQ) or similar curable layer and the metal pad is increased and the bondability is improved. Accordingly, the technology of improving the characteristic of device by preventing the problem that the metal pad is excessively opened in a subsequent curing process and the layer of a lower portion of the metal pad is attacked is disclosed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a division of U.S. application Ser. No. 12/129,769 filed May 30,2008, which claims the priority benefit under USC 119 of KR10-2007-0110685 filed Oct. 31, 2007, the entire respective disclosuresof which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and, moreparticularly, to a metal pad open process for manufacturing asemiconductor device.

In general, a pad is a part which is connected with a wire in a wirebonding process of the assembly process which forms a semiconductorchip, while a semiconductor device communicates signals between theinside and the outside through the pad.

In addition, in the manufacturing process of the semiconductor device,when a plurality of chips are prepared on wafers, a passivation layer isformed as a final protection layer in order to protect the chips from anundesirable environment. After the formation of the passivation layer,the pad is opened by removing the passivation layer on the pad in orderto connect a lead line which is to be connected with an outside circuitin the package process with the pad of chip.

FIGS. 1 a to 1 g are cross-sectional views showing the manufacturingmethod of a semiconductor device according to the related art.

Referring to FIG. 1 a, an intervening dielectric layer 105 and a metalpad 120 are formed over a semiconductor substrate 100. Here, a titaniumlayer 110 is formed under the metal pad 120, while a titanium nitridefilm 125 is formed on the metal pad 120.

Referring to FIG. 1 b, a passivation layer 130 is formed on an entiresurface including the metal pad 120.

Referring to FIG. 1 c, a first photoresist pattern (not shown) is formedover the passivation layer 130.

Here, it is preferable that the first photoresist pattern (not shown) isformed while the center of the metal pad 120 is opened.

Then, the passivation layer 130 is etched, using the first photoresistpattern (not shown) as a mask to expose the titanium nitride film 125,which is formed on the metal pad 120. Then, the first photoresistpattern (not shown) is removed.

Referring to FIGS. 1 d and 1 e, a curable polymide isoindroquirazorindione (PIQ) layer 135 is formed on an entire surface includingthe etched passivation layer 130.

A second photoresist pattern 140 is formed over the PIQ layer 135.

At this time, it is preferable that the second photoresist pattern 140is formed while the edge part of the etched passivation layer 130 is notopened.

Then, the PIQ layer 135 is etched, using the second photoresist pattern140 as a mask.

At this time, it is preferable that the PIQ layer 135 remains in theside wall of the etched passivation layer 130.

Then, the second photoresist pattern 140 is removed.

Referring to FIG. 1 f, a curing process is performed for the PIQ layer135.

The PIQ layer 135 is condensed by the curing process. Due to this, thePIQ layer 135, which was formed on the side wall of the etchedpassivation layer 130, retrogrades into the upper portion of thepassivation layer 130. Therefore, the region opened by the PIQ layer 135is widened.

At this time, the RIO layer 135 is unable to cover the area over theouter ring of the metal pad 120 in the curing process, and a liftingphenomenon (see ‘A’) is generated.

Referring to FIG. 1 g, the etching process is performed to remove thetitanium nitride film 125 on the metal pad 120, so that the metal pad120 is exposed.

FIGS. 2 a to 2 d are cross-sectional views showing another method ofmanufacturing a semiconductor device according to the related art.

Referring to FIGS. 2 a and 2 b, an intervening dielectric layer 205, ametal pad 220 and a passivation layer 230 are formed over asemiconductor substrate 200 with a method as illustrated in FIGS. 1 aand 1 b. A titanium layer 210 is formed under the metal pad 220, while atitanium nitride film 225 is formed on the metal pad 220

The passivation layer 230 is etched so that the passivation layer 230 ofa constant thickness remains over the metal pad 220 such that the metalpad 220 is not exposed.

A PIQ layer 235 is formed on the entire surface including the etchedpassivation layer 230.

Referring to FIG. 2 b, the PIQ layer 235 is etched in order that the PIQlayer 235 remains on aside wall of the etched passivation layer 230.

Referring to FIG. 2 c, when the curing process is performed for the PIQlayer 235, the PIQ layer 235 is condensed so that the opened region iswidened.

Here, while the PIQ layer 235 is condensed, the PIQ layer 235 formed onthe side wall of the etched passivation layer 230 retrogrades into thedirection in which the opened region is widened, so that it remains onlyover the passivation layer 230.

At this time, the lifting phenomenon A if the PIQ layer 235 isgenerated.

Referring to FIG. 2 d, the etching process for removing the titaniumnitride film 225 such that the passivation layer 230 remains over themetal pad 220 is performed.

At this time, a gap between the metal pad 220 excessively opened in theetching process generates an attack (see ‘B’) in the passivation layer230.

In the manufacturing method of a semiconductor device according to therelated art, there is a problem in that the metal pad is excessivelyopened due to the PIQ layer. Hence, the attack occurs in the subsequentPIQ layer etching process and the layer of the lower portion of themetal pad is damaged. Accordingly, the reliability of device is lowered.

BRIEF SUMMARY OF THE INVENTION

According to a first embodiment of the invention, a method formanufacturing a semiconductor device comprises: forming a metal pad overa semiconductor substrate; etching the metal pad to form a trenchdefining at least one side surface; forming a first protection layer onan entire surface including the metal pad; etching the first protectionlayer whereby the first protection layer remains on the trench; forminga curable second protection layer on an entire surface including theetched first protection layer and the trench; etching the secondprotection layer whereby the first protection layer on the metal pad isexposed and the second protection layer remains on a side surface of thetrench; curing the second protection layer; and etching the exposedfirst protection layer to expose the metal pad.

According to a second embodiment of the invention, a method formanufacturing a semiconductor device comprises: forming a metal pad overa semiconductor substrate, said metal pad comprising edge portions andan interior area bounded by the edge portions; forming a trench on alocation which is spaced from the edge portions of the metal pad intothe interior surface by etching the metal pad, said trench defining aside wall; forming a first protection layer on an entire surfaceincluding the trench; etching the first protection layer whereby thefirst protection layer remains over the metal pad; etching the firstprotection layer whereby the first protection layer remains on a sidewall of the trench; forming a curable second protection layer on anentire surface including the etched first protection layer; etching thesecond protection layer whereby the second protection layer remains overthe trench; curing the second protection layer; and etching the firstand second protection layers to expose the side wall of the trench andthe metal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 a to 1 g are cross-sectional views showing a manufacturingmethod of a semiconductor device according to the prior art.

FIGS. 2 a to 2 d are cross-sectional views showing a manufacturingmethod of a semiconductor device according to the prior art.

FIGS. 3 a to 3 g are cross-sectional views showing the manufacturingmethod of a semiconductor device according to a first embodiment of theinvention.

FIGS. 4 a to 4 i are cross-sectional views showing the manufacturingmethod of a semiconductor device according to a second embodiment of theinvention.

DESCRIPTION OF EMBODIMENTS

FIGS. 3 a to 3 g are cross-sectional views and perspective views showingthe manufacturing method of a semiconductor device according to a firstembodiment of the invention.

Referring to FIG. 3 a, an intervening dielectric layer 410 and a metalpad 420 are formed over a semiconductor substrate 400.

Here, a titanium nitride film 423 and a titanium film 415 are formed onand under the metal pad 420, respectively.

Referring to FIG. 3 b, a first photoresist pattern 425 is formed,opening a central portion of the metal pad 420.

At this time, preferably, in the first photoresist pattern 425, thecentral part is opened within the range that the edge part of the metalpad 420 is not exposed.

Referring to FIG. 3 c(i), the titanium nitride film 423 and the metalpad 420 are etched with the first photoresist pattern 425 as a mask toform a trench so that the central part of the metal pad 420 is concave,i.e., defines a trench.

Then, the first photoresist pattern 425 is removed.

A passivation layer 430 is then formed on an entire substrate includingthe trench formed in the metal pad 420.

Here, FIG. 3 c(ii) is a perspective view showing the formed metal pad420, showing that a concave trench is formed in the central part of themetal pad 420.

At this time, a step difference is generated in the edge part of themetal pad 420 with the trench.

Referring to FIG. 3 d, a second photoresist pattern (not shown) for arepair process is formed over the passivation layer 430. It is preferredthat the step difference which is generated in the either side of thetrench is not opened in the second photoresist pattern (not shown).

The passivation layer 430 is then etched using the second photoresistpattern (not shown) as a mask.

At this time, preferably, the passivation layer 430 remains on thesurface and sidewalls of the trench.

Then, the second photoresist pattern (not shown) is removed.

Referring to FIG. 3 e, a curable polyimide isoindro quirazorindione(PIQ) (or other suitable curable material) layer 435 is formed on anentire surface including the etched passivation layer 430.

A third photoresist pattern 440 is formed over the PIQ layer 435.

At this time, preferably, the third photoresist pattern 440 is formed inorder that a region which is smaller than the region which is exposedwith the etched passivation layer 430 is exposed.

Referring to FIG. 3 f, the PIQ layer 435 is etched using the thirdphotoresist pattern 440 as a mask.

At this time, it is preferable that the PIQ layer 435 remains on thesidewalls of the etched passivation layer 430.

Referring to FIG. 3 g, a curing process is performed for the PIQ layer435.

The passivation layer 430 remaining in the exposed area is etched andthe metal pad 420 is exposed.

At this time, the contact area between the PIQ layer 435 and thepassivation layer 430 is increased on the metal pad 420 due to the stepdifference (see ‘C’ in FIG. 3 g). The adhesive force between thepassivation layer 430 formed according to the step difference of thetrench and the PIQ layer 435 is improved. Thus, a lifting phenomenon ofthe PIQ layer 435 is not generated, and the metal pad 420 is notexcessively opened in the curing process, so that the generation ofattack is prevented in the etching process.

FIGS. 4 a to 4 i are cross-sectional views showing the pad openprocessing of a semiconductor device according to a second embodiment ofthe present invention.

Referring to FIG. 4 a, an intervening dielectric layer 510 and a metalpad 520 are formed over a semiconductor substrate 500.

Here, it is preferable that the intervening dielectric layer 510comprises an oxide layer, while a titanium nitride film 523 and atitanium film 515 are formed on and under the metal pad 520,respectively.

Referring to FIG. 4 b, a first photoresist pattern 525 is formed overthe metal pad 520.

At this time, preferably, in the first photoresist pattern 525, an openregion in the shape of a cylinder or a parallelepiped is implemented ina location which is spaced respectively from the edge part of both sideof the metal pad 520 into an inner side.

Referring to FIG. 4 c(i), a trench is formed by etching the metal pad520 with the first photoresist pattern 525 as a mask.

Here, it is preferable that the trench is formed in the shape of acylinder or a parallelepiped in a location which is spaced apartrespectively from the edge part of both sides of the metal pad 520 intothe inner portion of the metal pad 520.

Referring to FIG. 4 c(ii), which is a perspective view showing the metalpad 520 in which the trench is formed, it is shown that the trench of acylinder or parallelepiped shape is implemented in a location which isspaced from the edge portion of both sides of the metal pad 520 into theinner portion thereof.

Here, preferably, a plurality of trenches of the cylinder type areimplemented along an edge portion of the metal pad 520.

In addition, it is preferable that the trench of a parallelepiped shapebe implemented in a direction parallel to the edge part of the metal pad520.

Then, the first photoresist pattern 525 is removed.

Referring to FIG. 4 d, a passivation layer 530 is formed over an entiresurface including the trench.

A second photoresist pattern (not shown) is formed over the passivationlayer 530.

At this time, it is preferable that the central part of the metal pad520, which includes the two trenches, is formed to be exposed in thesecond photoresist pattern (not shown).

The passivation layer 530 is etched with the second photoresist pattern(not shown) as a mask.

At this time, preferably, the passivation layer 530 remains over themetal pad 520.

Then, the second photoresist pattern (not shown) is removed.

Referring to FIG. 4 e, a third photoresist pattern 540 is formed overthe etched passivation layer 530.

Here, it is preferable that the third photoresist pattern 540 is formedin order that a plurality of trenches are opened, while the line widthis smaller than the line width of the trench.

Referring to FIG. 4 f, the passivation layer 530 is etched using thethird photoresist pattern 540 as a mask.

At this time, preferably, the passivation layer 530 remains along thesurface of the trench in order that the edge portion of the metal pad isnot exposed.

Referring to FIG. 4 g, a PIQ or similar curable layer 535 is formed overan entire surface including the trench.

Referring to FIGS. 4 h and 4 i, a fourth photoresist pattern (not shown)is formed over the PIQ layer 535.

Here, it is preferable that the central part of the metal pad 520 isformed to be opened in the fourth photoresist pattern (not shown),whereas the plurality of trenches are not opened.

The PIQ layer 535 is then etched using the fourth photoresist pattern(not shown) as a mask.

At this time, the PIQ layer 535 remains on the sidewalls and the bottomof the etched passivation layer 530.

The PIQ layer 535 of the opened region, the passivation layer 530, andthe titanium nitride film 523 are then etched to expose the metal pad520.

At this time, preferably, the passivation layer 530 of the sidewalls ofthe trench is not etched.

Here, the trench of a cylinder or parallelepiped shape is generated (see‘D’ in FIG. 4 i). Therefore, a phenomenon occurs wherein the contactarea between the passivation layer 530 formed along the step differenceof the metal pad 520 and the PIQ layer 535 is increased, and theadhesive force thereby increases so that the PIQ layer 535 isexcessively opened is prevented.

Here, since the metal pad 520 is not excessively opened, an attackgenerated in the passivation layer 530 in the etching process can beprevented.

The invention has the effect that the metal pad is etched to form atrench which has a step difference so that the contact area between thepassivation layer and the curable polymide isoindro quirazorindione(PIQ) or similar material layer is increased and the bondability isimproved, and the problem that the metal pad is excessively opened inthe subsequent curing process and the layer of the lower portion of themetal pad is attacked in the subsequent etching process is prevented.

The foregoing embodiments of the invention are illustrative and notlimiting. Various alternatives and equivalents are possible. Theinvention is not limited by the type of deposition, etching polishing,and patterning steps described herein, nor is the invention limited toany specific type of semiconductor device. For example, the presentinvention may be implemented in a dynamic random access memory (DRAM)device or non volatile memory device. Other additions, subtractions, ormodifications of the disclosure are intended to fall within the scope ofthe appended claims.

1. A method for manufacturing a semiconductor device comprising: forming a metal pad over a semiconductor substrate, said metal pad comprising edge portions and an interior area bounded by the edge portions; forming a trench on a location which is spaced from the edge portions of the metal pad into the interior surface by etching the metal pad, said trench defining a side wall; forming a first protection layer on an entire surface including the trench; etching the first protection layer whereby the first protection layer remains over the metal pad and on a side wall of the trench; forming a curable second protection layer on an entire surface including the etched first protection layer; etching the second protection layer whereby the second protection layer remains over the trench; curing the second protection layer; and etching the first and second protection layers to expose the side wall of the trench and the metal pad.
 2. The method according to claim 1, further comprising forming an intervening dielectric layer between the semiconductor substrate and the metal pad.
 3. The method according to claim 2, wherein the intervening dielectric layer comprises an oxide film.
 4. The method according to claim 1, wherein the second protection layer comprises a polymide isoindro quirazorindione (PIQ) layer.
 5. The method according to claim 1, wherein the trench includes a plurality of sub-trenches.
 6. The method according to claim 5, wherein the sub-trenches are substantially in the shape of a cylinder or a parallelepiped. 